In reply to ben@SystemVerilog.us:
Hi Ben,
First of all, thank you so much for correcting my code. I thought something but wrote down something else. It was the biggest blunder. The updated form is working, right? I ran it and your solution on eda-playground and I didn’t notice any difference.
Actually, your solution seemed a little bit intricate to me. That’s why I tried to write the assertion with the techniques I have learned.
One more thing, the waveform you shared where your solution and my assumption can be observed clearly, over there I noticed one thing. In my case, ok2 is not exactly presented as ok signal. You also can notice that. Is that any kind of fault or something else?