In reply to ben@SystemVerilog.us:
Hi ben ,
Can we go with the following way ?
module test;
bit busy, clk;
bit[0:8] max;
assert property (p1);
property p1;
int count = 0;
@(posedge clk) $rose(busy) |-> first_match((busy , count = count+1)
[*1:$] ##1 $fell (busy)) ##0 (count <= max);
endproperty
endmodule