In reply to ben@SystemVerilog.us:
Thanks Ben.
This way, I have modified my assertion as below and it is working properly.
sequence s1(d1);
int v;
((1, v=d1) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
endsequence
sequence s2(e1,maxi,sq);
int v1,diff;
((1,v1=e1,diff=maxi-1) ##0 s1(1) ##0(diff>=0, diff=diff-1) [*1:$] ##0sq);
endsequence
assert property (@(posedge clk) $rose(busy) |-> s2(1, max, $fell(busy)))
Thanks a lot.