In reply to ben@SystemVerilog.us:
Ben,
A follow-up question. I made some changes to the code such that the antecedent is multi-threaded : edalink2
EDIT: Added changes to the code such that rdDone is 0 from T:34 to end of simulation.
( Previously rdDone was true from T:34 to end of simulation )
The expectation is that since sequence: ##5( wData == ( local_data + 'hFF ) ) is True at T:85 and T:105 , I expected the assertion to pass twice.
Once at T:85 and other at T:105 , however I observe that assertion passes only once at T:105.
Any suggestions on why is it so ?