Local variable assignment in Multithread consequent

SystemVerilog
,
2

In reply to MICRO_91:
Your property is expanded to


property p_check; 
       int  local_data;
       RdWr |-> 
             ##[1:5] (rdDone, local_data = rData) ##5  
             wData == local_data + 'hFF; 
       endproperty 
// As you expressed, it is multithreaded; thus you have the consequent as 
(##1(rdDone, local_data = rData) ##5 wData == local_data + 'hFF) or 
(##2(rdDone, local_data = rData) ##5 wData == local_data + 'hFF) or 
(##3(rdDone, local_data = rData) ##5 wData == local_data + 'hFF) or 
(##4(rdDone, local_data = rData) ##5 wData == local_data + 'hFF) or 
(##5(rdDone, local_data = rData) ##5 wData == local_data + 'hFF)

The success of any one thread concludes the assertion.
A failure would occur if none of the ORed thread are a match (BTW, sequences match or do not match; properties are true or false; assertions pass or fail)

Comments on your style:

  • Reduce the number of parentheses, use only what is really needed; it makes the code hard to read.
  • You have too many unneeded character and line spaces.
  • You have too many sequence declarations that are not really needed.

I recommend that you read my paper on Underdatandin the SVA Engine.

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or https://rb.gy/ibks5p

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