Hi,
I’m wondering if there’s any places to practice verification questions in systemverilog like a SW engineers can solve riddles on leetcode.
I would be cool to solve problems that would come up more so in verification than in SW, like having to write a particular constraint, or drive particular patterns.
There are many adhoc efforts in creating such - atleast as case studies, interview Qs etc. But I am not aware of a dedicated portal for it. IMHO this very forum/portal should fill that gap via a separate page - hope @dave_59 and other GODs of VA would hear us soon! For now, look up Sweety Pinjani on LinkedIn as she shared some interesting challenges. @ramdas_mozhikunnath_amd and Robin garg wrote a book on this topic, that might be of some interest (though not a direct LeetCode replacement) meanwhile.
Dave - access to tools is only one-part of the problem. From what I understand LeetCode is lot more than that. Around DAC last year I was exploring if Accellera would be willing to drive an initiative to offer some sort of accreditation/certification to address similar requests from hiring managers & job seekers, but not much luck! I am hoping Siemens EDA/VerifAcacdemy can help the industry here!
Thanks