In reply to ben@SystemVerilog.us:
Thank you Ben, appreciate it.
I came up with another method too by using variable
sequence seq1(wu_state, M);
int cnt;
(state == 0,cnt=0) [*1:$] ##1
(state == 1) [*1:$] ##1
(state == 2,cnt++) [*1:$] ##0
(M==cnt) ##1
(state == 3) [*1:$] ##1
(state == 4) [*5] ##1
(state == 5) ;
endsequence
What do you think?