Kindly revert me a exact behaviour of for loop by changing the "#0 delay" position for the below code

SystemVerilog
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4

In reply to Sriram Yalavatti:

Hi,

Doubt 1.
Nobody predict the order of threads which are scheduled in same time slot.
This is because SystemVerilog/VHDL are for Hardware design, not software.
In Hardware world, nobody knows the order of simultaneous events.
You should keep it in your mind.

Doubt 2.
These behaviors are correct.
The key to understand these behavior is - in which timeslot (when) is “i++” executed.

  • same time slot as $display, or
  • one time slot later (because of #0) from $display.