In reply to kitanisi:
In reply to Sriram Yalavatti:
Hi,
Doubt 1.
Nobody predict the order of threads which are scheduled in same time slot.
This is because SystemVerilog/VHDL are for Hardware design, not software.
In Hardware world, nobody knows the order of simultaneous events.
You should keep it in your mind.
Doubt 2.
These behaviors are correct.
The key to understand these behavior is - in which timeslot (when) is “i++” executed.
- same time slot as $display, or
- one time slot later (because of #0) from $display.
- one time slot later (because of #0) from $display.
“#0” shouldn’t advance into the next time slot, correct?
Isn’t it more of scheduling the event to be processed in the in-active region (same time slot)?
I’m guessing the reason for print “2” is because “i” has a global scope, and both processes seem to be updating it. Am I interpreting it incorrectly?