Issues while connecting port in class hierarchy to a module having imp

UVM
,
6

In reply to MICRO_91:

Hi,

After checking, I agree with you about the phasing approach.
About your problem, the my_class component is not a part of “env” component hierarchy, then the order execution of leaf1’s build_phase and my_class’s build_phase cannot be identified. In your case, the my_class’s build_phase was executed before leaf1’s build_phase, that’s why you could not get what you want in build_phase of my_class component.

If you move the uvm_config_db#(…)::get(…) statement of my_class component to other phases which are executed after build_phase (such as connect_phase, etc.), you will be able to get your port.
Example:


class my_class extends uvm_component ;
  ...
  function void connect_phase(uvm_phase phase);
    uvm_blocking_put_port #(trans) put ;
    if(uvm_config_db#( uvm_blocking_put_port #(trans) )::get(this,"","ENV",put) )  // [B] 
    begin  
      put.connect( imp ) ; 
    end
    else
    begin
      `uvm_error("CONFIG_DB_GET","GET Failed")  // Fails but why ??
    end
  endfunction
endclass

I hope this will help.