Issues while connecting port in class hierarchy to a module having imp

In reply to MICRO_91:

First, you need to use “create” method to create these components.
Second, your my_class is not a part of env hierarchy. When you call run_test(“env”), uvm will traverse all components which are children of env component and execute their phases in order from build to final.
Since my_class is not a child of env component, I think there is no way all phases of my_class can be called.

You should create a test component where env, my_class are children, then you call run_test(“test”).