Issue with using set_inst* and set_type* override

UVM
1

Hi,

I currently have a component (named ‘sequencer’), which I want to be replaced with another component (name ‘proj_sequencer’) whenever an instance of type ‘sequencer’ is created.

I have tried implementing the code shown below and I am stuck with compile error. [MFNF] Member not found i.e. class member ‘a’ for the extended class.

However when I comment the line

env.sqr.a = 5;

I can see the environment hierarchy printed as expected with the overidden class type.

Would appreciate if anyone could point out where I am going wrong, and what is wrong with my approach.

Everything in reference to below sample code

// Base Sequencer
class sequencer extends uvm_component;
`uvm_component_utils(sequencer)
function new(string name = "sequencer", uvm_component parent);
  super.new(name, parent);
endfunction
endclass

// Project Sequencer
class proj_sequencer extends sequencer;
int a; // Added class member
`uvm_component_utils_begin(proj_sequencer)
  `uvm_field_int(a, UVM_ALL_ON)
`uvm_component_utils_end

function new(string name = "proj_sequencer", uvm_component parent);
  super.new(name, parent);
endfunction
endclass

// Environment
class top_env extends uvm_env;
`uvm_component_utils(top_env)
sequencer  sqr;
function new(string name = "top_env", uvm_component parent);
  super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  sqr = sequencer::type_id::create("sqr", this);
endfunction
endclass

// Top Test
class top_test extends uvm_test;

`uvm_component_utils(top_test)
top_env env;

function new(string name = "top_test", uvm_component parent);
  super.new(name, parent);
endfunction

virtual function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  set_type_override_by_type(sequencer::get_type(), proj_sequencer::get_type());
  env = top_env::type_id::create("env", this);
endfunction

virtual function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);
endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);
  super.end_of_elaboration_phase(phase);
  env.sqr.a = 5;
  env.print();
endfunction

endclass

Thanks

2

There is no code posted. Please provide a complete example which demonstrates your issue.

3

Apologies. It seems there was some issue while posting.
I have updated original post.

Also, kindly disregard the poor choice of class names i.e. ‘sequencer’ and ‘proj_sequencer’.
The original idea is basically having two components.

Thanks

4

Your environment is coded to use the base ‘sequencer’, which is why you can’t access ‘a’ which exists only in ‘proj_sequencer’.

You can check the type of ‘sqr’ using casting and then access ‘a’ based on the type.

2 Likes
5

Understood. Thanks