Issue with $stable when used with reject_on

SystemVerilog
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3

In reply to hisingh:
Add clocking event in the $stable


 reject_on( ! $stable( Sig1, @(posedge clk) ) )  $stable( Sig1 )  s_until_with  $rose( Sig2 )  ;

The reject_on (expression_or_dist) property_expr rejects the property as false if the abort condition is true. Otherwise, with the abort condition as false, the property expression evaluates to completionlog]