Issue with constraint

SystemVerilog
,
6

In reply to rag123:

My mistake, it’s 1 in 33

solution # var1 var2 var3
1 2 0 0
2 3 0 0
3 3 0 1
... 3 0 ...
17 3 0 15
18 3 1 0
19 3 1 1
... 3 1 ...
33 3 1 15