Issue with constraint

SystemVerilog
,
3

Here is one way to slove your problem. There are some syntax mistakes in the above question. you haven’t declared var1 and var2 as bit data type. You can put all conditions in one constraint

class base;
rand bit [1:0]var1;
rand bit [3:0] var2;
rand bit var3;
constraint cnt1 {soft var1 inside {2,3};
                (var1==2) -> (var2==0 && var3==0);
                solve var1 before var2;}
endclass

module my_module;
  base obj;
  initial begin
    obj=new();
    repeat(10) begin
      obj.randomize();
      $display("var1=%d,var2=%d,var3=%d",obj.var1,obj.var2,obj.var3);
    end
  end
endmodule

Here is the expected output.
var1=2,var2= 0,var3=0
var1=3,var2= 7,var3=0
var1=2,var2= 0,var3=0
var1=2,var2= 0,var3=0
var1=3,var2= 4,var3=0
var1=3,var2=11,var3=0
var1=2,var2= 0,var3=0
var1=3,var2=13,var3=1
var1=2,var2= 0,var3=0
var1=3,var2= 4,var3=1