Issue with Constraint Solver

SystemVerilog
,
3

In reply to soumyarayaprolu:

Constraints are working just fine. Can you give the scenario for which you are getting unexpected results?

module test;

  class A;

    rand bit[3:0] max_val;
    rand bit[7:0] bin[8];
    rand bit[1:0] if_yes;

    rand int a, b;

    constraint c1 {
      (32 * max_val + 'd480) == a;
    }

    constraint c2{
      (
      'd96 + bin[0] + bin[1] + bin[2] + bin[3] + bin[4] + bin[5] + bin[6] + bin[7] +
      ((if_yes == 1)? 5 : ((if_yes ==2)? 2: (if_yes == 3)? 4:0))
      ) == b;
    }

    constraint c3{
      a > b;
    }

  endclass

  A a_h;

  initial
  begin

    a_h = new();

    repeat(10)
    begin
      assert(a_h.randomize());
      $display("%0d -- %0d -- %p", a_h.max_val, a_h.if_yes, a_h.bin);
      $display("%0d -- %0d", a_h.a, a_h.b);
    end
  end
	
endmodule