Is there any recent book as good as SystemVerilog for Verification?

SystemVerilog for Verification is a good book.
But some parts are outdated.
For example, a lot of examples are still using program block which is not recommended nowadays.

Is there an alternative?

Question: What are you looking for?

  • For formal verification, see my review (ambenji) of the book
    Formal Verification: An Essential Toolkit for Modern VLSI Design 2nd Edition
    by Erik Seligman (Amazon)

  • On SV Verification, the best resources are replies to actual users’ questions that
    address real issues in the application of the language.

  • Conference and vendors’ papers are additional resources for useful techniques and applications.

(On my end, check out my papers that address users’ issues and applications of SV and SVA).
Ben Cohen
Link to the list of papers and books that I wrote, many are now donated.

I look for a book that is good for a complete beginner in verification and systemverilog.