In reply to vickyvinay:
My understanding, in a nutshell, is that you should use the checker to group up your assertions instead of using a module.
From the LRM:
The checker construct in SystemVerilog was
specifically created to represent such verification blocks encapsulating assertions along with the modeling
code.
I really suggest you back to the LRM, you can download/buy it from the IEEE website.
Another place where I found useful information about this topic is the following course: https://www.udemy.com/course/systemverilog-assertions-language-and-applications/
Cheers,
Stef