Is there a way to use SVA property's local variable value to be used outside property

SystemVerilog
9

One time I used a function with static variable to enable communication between assertion threads. Worked well in that case. Maybe someone will use this concept, and I’m also wondering what you will think of it. Here is the code extract:


function void count_sync(output int o_counter, input bit reset);
    static int counter = 0; 
    begin
    counter = reset ? 0 : counter+1;
    o_counter = counter;
end
endfunction

property sync_processed;
    int counter = 0;
    ( seq_single(k28_5, k30_7, d0_6) , count_sync(counter, 0)) |->
        (counter == 3) |-> ##1 ($rose(asic_rst) ##1 $fell(asic_rst), count_sync(counter, 1));
endproperty