Is there a way to use SVA property's local variable value to be used outside property

SystemVerilog
6

Hello Everyone,

I have a similar situation where I need to use the local variable of my property inside the sequence which it calls. But this is not allowed by SVA.
Below is my requirement :

  sequence seq_timer_irq_to_fccu;
    ($rose(Ctrl[16])) ##1 (1,timer=timer-1'b1) [*0:$] ##1 timer==0 ##0 ($rose(timer_irq) && $rose(TmrIrq_status[0]));
  endsequence
  sequence seq_timer_irq_internal;
    (!(Ctrl[16])) ##1 (1,timer=timer-1'b1) [*0:$] ##1 timer==0 ##0 (!(timer_irq) && $rose(TmrIrq_status[0]));
  endsequence
  property ASSERT_TIMER_IRQ;
    int timer = 0;
    @(posedge ipg_clk) disable iff (async_reset_b == 1'b0)
    (($rose(Ctrl[0])) && !timer_irq, timer=TmrReLd+1'b1) |-> (seq_timer_irq_to_fccu or seq_timer_irq_internal); // TmrReLd is local signal inside my interface which is connected to the RTL top.
  endproperty

The above code is giving syntax error which I expect here. Could anyone please suggest me how can I achieve my goal here.