Is there a way to use SVA property's local variable value to be used outside property

SystemVerilog
12

In reply to M_Dave:

Another example using the idea of Ben. Thanks
In this case i do not use the uvm macros and the property is measuring the time a signal (SHIFT_LATCH) is being zero.




function void report_fail(time cur_time, time neglatch_leading, time min_latch_time_ps);
        //error condition BAD CASE
        if ((cur_time-neglatch_leading)<=min_latch_time_ps) begin
            $display("DEBUG_ERROR property_latch_too_short  at %t with  measured latch_time:%t and MIN_LATCH_TIME_PS:%t negedge latch time:%t \n", cur_time, cur_time-neglatch_leading ,min_latch_time_ps, neglatch_leading);
        end
endfunction

 property property_latch_too_short;
        time leading;
        disable iff(!SHIFT_RESETn)
            @(negedge SHIFT_LATCH)
            (1, leading = $time) |->
            @(posedge SHIFT_LATCH)
            (1, report_fail($time,leading,MIN_LATCH_TIME_PS)) ##0    //adding this to the last good case condition allows you print ONLY IN CASE OF ASSERTION CONDITION failure
            ((($time-leading)>MIN_LATCH_TIME_PS),  $display("property_latch_too_short  at %t with MIN_LATCH_TIME_PS:%t and measured latch_time:%t \n", $time, MIN_LATCH_TIME_PS, $time-leading));//GOOD CASE
endproperty
// FUNCTIONAL COVERAGE
c_property_latch_too_short: cover property(property_latch_too_short);
//ASSERTION OF PROPERTY
a_property_latch_too_short : assert property (property_latch_too_short)       else $error($sformatf("UVM_ERROR  Width of LATCH less than %t ps. Min Latch time violation at time %t",MIN_LATCH_TIME_PS,$time) );