Is there a dummy simulation that I could use to compare runtime of different machines

SystemVerilog
1

I would like to compare performance of different machine for the runtime of simulation.
I don’t want to use my own simulations because I would like to be able to share the simulation to siemens for instance if there is a problem of performance.
are there in verification academy some simulation example enough complex so that simulation could last minimum 30 minutes for instance ?

2

None of the examples in the Verification Academy Cookbook have simulations over 30 minutes, although it should be easy to modify them to make them run longer.

However, performance issues are best dealt with using your own design. It’s most likely a result of your coding style, and you need to use your tool’s profiling analysis features to find the problem areas.

This Siemens sponsored public forum is not for discussing tool specific issues. Please read your tool’s User Manual or contact your tool vendor for support.

3

thanks. I don’t have performance issue. I would like to compare performance of a linux server versus comme windows machines for instance. I need a “reference” test for this.
do you have a link for verification academy cookbook ?

4
5

Thanks a lot for the link. I found “Peripheral style design, programmed via registers” that is UART UVM test that has the perfect complexity :

Simulation are very short so I tried to increase the simulation time of the simulation called : rx_errors_int_test by modifying the file

./virtual_sequences/rx_errors_int_vseq.svh

before: repeat(64) begin
after: repeat(640) begin

but the UART is simulated (UART transmisssion) as long as before the modification but the simulation don’t stop. After UART signals moving correctly, UART is now stuck and the simulation never ends.

it seems that my modification is incorrect. Is anyone expert enough about this example to help me increase the simulation time of this simulation ? the goal is to have the UART be simulated much longer.

6

The virtual sequence you are referring to is used as part of a test to demonstrate some error scenarios. You will notice that it in the Makefile that specific test is not run as part of the regression. Increasing the run time is something that likely wasn’t tested, so you should focus only on the valid tests.