In reply to Gokul S:
This a a very broad question and answers to it will be highly opinionated. Here is my take:
SystemC is a library on top of an existing programming language, C++. It’s original goal was to provide hardware modeling concepts from Verilog and VHDL into a C++ environment. A few key hardware modeling concepts are:
- bit-level data types and operators on those types
- a scheduling algorithm that simulates massive amounts of concurrent threads
- module hierarchy with signal connectivity.
You can model at a much higher level of abstraction and get much better performance than you can in Verilog. However, if you model at the same level of abstraction that you do in Verilog, you may have worse performance.
SystemVerilog is a hardware description and verification language that added concepts from C and Java into Verilog, as well as a number of verification concepts, like assertions, functional coverage, and constraint randomization from other sources.
SystemC was available in production a number of years before SystemVerilog, but both became IEEE standards in the same year (2005).
The UVM is a base class library that adds some of the concepts from SystemC, like transaction-level modeling, and reporting. (coincidentally, there was some overlap in the people the contributed to both SystemC and UVM)
If you want some more information on trends in verification, please check here: