Is OK, in my situation, for a driver to have an analysis port or for a monitor to drive an interface signal?

In reply to aarelovich:

My suggestion would be not to mix and match the operations of driver with monitor and vice-versa.

a. Say if you are porting your bench to the SoC level, in that scenario you don’t want the driver/sequence active components and you tend to disable them. So in that case, your scoreboard will be expecting some data for checking process and will get stuck since your components are in passive mode.

b. Instead if you have your monitor by default as per basic flow, irrespective whether you agent is in active/passive mode, the monitor keeps monitor the data and sends it to the scoreboard for checks.

So for portability from IP/Subsystem Verification to SoC verification, its better to have them separate and do their functionalities separately and not to mix them.