Is it not allowed to use $sformat inside generate statement?

SystemVerilog
3

In reply to dave_59:

In reply to desperadorocks:
You are allowed to use $sformat inside a generate block, but the statements inside the generate block are not procedural unless you put it into that context. For example, you can use an initial block inside the generate.

generate
for (ganvar num = 0; num < 12; num++) begin
strong out_str; // this declaration has to be inside the for-loop
initial begin
$sformat(out_str, "`HELLO.fruit_num%0d", num);
hello_if.fruit[num] = out_str;
end
end
endgenerate

If you want to keep the continuous assignment, then you need to use $sformatf

generate
for (ganvar num = 0; num < 12; num++) begin
assign hello_if.fruit[num] = $sformatf("`HELLO.fruit_num%0d", num);
end
endgenerate

Hi dave_59,

This solution will work for UVM testbench. What if we want to use $sformat and $sformatf in formal testbench where only synthesizable constructs will be allowed?

Thanks.