We are trying to implement outstanding AXI writes via RAL i.e we send AWAddr & WData (single beat) without waiting for it’s BResp.
The basic idea stems from a paper suggested by you in user-defined-frontdoor-v-s-uvm-frontdoor
When using user-defined front door the UVM internally calls start for user-defined frontdoor sequence for each call to reg.write
// ...VIA USER FRONTDOOR
if (map_info.frontdoor != null) begin
uvm_reg_frontdoor fd = map_info.frontdoor;
fd.rw_info = rw;
if (fd.sequencer == null)
fd.sequencer = system_map.get_sequencer();
fd.start(fd.sequencer, rw.parent); // start is called for each call to write
end
Task ‘start’ would end as soon as finish_item(req) unblocks within body()
We want to update the mirrored value when the BResp is received