Invalid open array handle while passing an open array from c++ to system verilog

SystemVerilog
4

In reply to kartik:

Your prototype has 7 arguments, and your actual call has 8 arguments, an extra pkt_data_size argument.

Assuming pkt_mod_req.data is declared as logic [15:0] data, then you need to do

pkt_mod_req.data = new[N]; before calling seq_build_get_mxi_wpi_pkt(), where N is large enough to hold the packet you want to write out.