Interface issue

SystemVerilog
9

Is there any way to connect the simple interfaces to the array of interfaces in System Verilog.

The example snippet is follows.

// -------- INTERFACE --------
interface my_if;
    logic   d;
endinterface

// -------- INTERMEDIATE MODULE --------
module intermediate(
    my_if   i1,
    my_if   i2
    );

    sub mySub(
        .a   ('{i1,i2})// With this type of connection getting the syntax error on '{i1,i2} .
        .w1  (1'b1)
    );
endmodule

// -------- SUB MODULE --------
module sub(
    my_if         a[2],
    input wire    w1
    );

    assign a[0].d = w1;
    assign a[1].d = ~w1;
endmodule