Interface issue

SystemVerilog
2

Here there are two problems. First, Signals defined in mem_if does not have the direction. You need to use assign statement to connect. Second, data signal is bidirectional.

Example:

mem_if mem0if();
    assign mem0if.reset = Reset;
    assign mem0if.clock = Clock;
    assign mem0if.enable = Enable[0];
    assign mem0if.addr = Addr[7:0];
    //assign mem0if.data = Data;  //  This has to be taken care with more combo logic.
    assign mem0if.rwn = RWn;