Interface in uvm_test

UVM
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6

In reply to nchakravarthy:

Hi Julette,
There are two points to get the interface in the test case:

  1. The interface must be set in the general way in the tb_top in UVM, so over there set the interface as uvm_config_db #(virtual int_if):: set (uvm_root::get, “*”, “intf_hand”, int_if_hand); , this statement does you to get the interface to both higher and lower components in the VE.
  2. Now you can use it directly using get success = uvm_config_db #(virtual int_if)::get(this, “”, “intf_hand”, int_if_hand);
  3. My concern why do you want to set the interface again in the test case build_phase,
    I think so that you have already got the interface and could use the same to
    drive any signals on to the interface.
  4. uvm_config_db #(virtual interface int_if)::set(this, “”, “” ,int_if_hand.vif); syntax is wrong it should be #(virtual int_if) and set has the following arguments set(context,“instance_path”,“string_name”,variable_name).
    Thanks,
    Nikhil

what about test cases extended from base test
i done as below but getting error

ex class test_case2 extends base_test;
virtual lbus_if lbus_vif;
//function new
//start of simulation phase
//build phase
$assertoff(lbus_if.cssss);

endclass: test_case2