Hello Thank you for your replies.
indeed my memory wrapper IP which holds these two top level modules ( single and dual port memories ) have almost the same pinlevel interfaces except the memory signals which are addr, wr_en; rd_en; wdata; rdata in case of single port mem while for the dual port memory design we have the same signal but twice for each port A & B (addr_a ,addr_b ,wr_en_a,wr_en_b etc…)
I have already built the uvm environment for my memory wrapper but for now it supports only the single port memory model and I really don’t want to duplicate all of the components ( agent , scoreboard etc ) I have already created.
I just want to find a way to make the actual testbench used to verify both designs, is that feasible ?