Input Sampling for Clocking blocks

SystemVerilog
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2

In reply to Have_A_Doubt:

You first statement is correct, but the rest might help by understanding there are actually three different values associated with a clocking block input signal.

  1. The raw signal value determined by what is driving the signal.
  2. The sampled signal value determined by the sampling skew.
  3. The clocking block variable (clockvar) that gets updated at the clocking event to the sampled value.

It’s possible for there to be three different values at a point in time. I think you are confused by the difference between the sampled value and the clocking block variable that gets updated to hold the sampled value.

Note that the LRM text you quoted has a number of clarifications in the next revision of the standard.