In reply to Witty:
Think of arrays of arrays instead of multi-dimensional arrays. Most SystemVerilog methods that operate on unpacked arrays only deal with one dimension at a time. You can do
(noddy.exists(4) && noddy[4].exists(6))
And because SystemVerilog has expression short-circuiting, if the first term is false, the second term never evaluates. So that avoids an invalid reference.