In reply to raku:
Put the display before clock edge and see if spi_cs is 0 or not.
while (ifc.spi_cs == 1'b1 )
begin
$display("Inside while: the value of ifc.spi_cs is %d", ifc.spi_cs);
@ (posedge ifc.spi_sck )
end
Also I think CS and synchronized with posedge of CLK thats why Delay is not captured by simulation.
Solution1 :
while (ifc.spi_cs == 1'b1 )
begin
$display("Inside while: the value of ifc.spi_cs is %d", ifc.spi_cs);
@ (negedge ifc.spi_sck )
end[
Solution2 :
while (ifc.spi_cs == 1'b1 )
begin
$display("Inside while: the value of ifc.spi_cs is %d", ifc.spi_cs);
@ (posedge ifc.spi_sck )
#0 //This will remove delta delay issue if its there.
end[