In reply to pablo.tomaz:
The problem is that SystemVerilog is used as both a Hardware Description Language and a Testbench Language (as well as a few other purposes). Loop-unrolling is something a synthesis tool does. But a simulation tool does not distinguish between what is supposed to be synthesized or not. So the rules for the language are based on how a programming language needs to implement the functionality without understanding what the code is trying to do.
A generate for-loop is the way you tell the compiler to unroll the loop. So you can write your code as
for(genvar I = 0; I < $clog2(WIDTH); I++) begin : outer_loop
always_comb
for(int j = (2**i), k = 0; j < $clog2(WIDTH); j = j + (2**(i + 1)), k = k + (2**i))
begin : inner_loop
dat_masks[i][k +: 2**i] = i_dat[j +: 2**i];
end : inner_loop
end : outer_loop