In reply to srbeeram:
Could you please clarify what is timeslot in system verilog regions?
and when @(posedge clk) is executed in system verilog regions?
and when NBA is executed? is it before the posedge of the clock or after the posedge of the clock ?
or NBA is executed for each timeslot?
See my paper that explains the timing regions and demonstrates graphically what is processed when in a time step.
To answer your question, if clk was 0 and is assigned a 1 at t100, then
t100 represents a time step. Code following the @(posedge clk) is processed in the Active region.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog