From the SystemVerilog point of view, you are never required to call the super method of any base class method except the constructor, new(). When extending a class method, you need to know what functionality would be missing if you didn’t call the super method by looking at the source code for the base class (or the documentation for that class)
For classes extended directly from uvm_component, the only phase method that has any functionality in it is the build_phase(). And that functionality is only needed if you use the `uvm_field macros, which we strongly recommend against using do to the very poor performance they have.