In reply to cgales:
In reply to UVM_LOVE:
I believe that this is demonstrating issues that when a sequence accesses registers using legacy methods (i.e. getting a register address and then reading/writing that address), the register model won’t be kept up to date.
You need to ensure that all of your sequences use the reg_map.register.XXX() methods to maintain register coherency.
Yep, but I found similar explain about the issue as the below,
Here also said about Disadvantage - It can not update the register model if register sequences are written to access DUT registers.
From here Also I’m confused that eventually reg.write() and reg.read() will update “reg”.
But why this article say that a sequence of reg.write() and reg.read() not update the “reg”?
I think this is the reason of predictor absence, If yes, Is there any workaround method for resolving this except explicit method?