In reply to rohit_kumar:
One of the goals of UVM is abstracting all of the physical timing information away from the testbench and keep everything in terms of transactions. That means the only timing delay in your testbench should be in the specification of your clock cycle and no other event controls, except waiting for a clock edge to synchronize with in the direct interface to your DUT.
Simulation using hardware emulation relies heavily on these techniques to get maximum performance. You many want to see some of the modeling guidelines in use for that:
https://verificationacademy.com/courses/systemverilog-testbench-acceleration