I2C protocol implementation

SystemVerilog
1

I am working on a project involving the I²C protocol, and I need some help regarding clock frequency implementation in our design.

Here’s the setup:

  • We have two masters communicating with a 128-byte memory slave.
  • Each master has its own FIFO to store instructions if the bus is busy, and a round-robin arbiter grants access to the bus.
  • The master clock frequency is 1 MHz, and each master generates a read/write instruction for the slave every 25 microseconds.
  • The I²C bus clock, driven by the masters, operates at 400 kHz.

I’m unsure how to properly align these frequencies in the design. Should the FIFO or arbiter logic be modified to account for the differences, or is there a simpler way to handle this? Are we over-complicating the design?

2

I don’t know the specifics of your design, but I don’t understand your use of an arbiter to grant access to the bus. The I2C protocol has built-in collision detection which a master should be using to determine if there are two masters attempting to access the bus at the same time. There should be no need for any arbitration, and each master should be able to access the bus when the previous transaction has completed.