I would like to control no.of ones and zeros in a particular dynamic array by using constraint?

SystemVerilog
,
5

In reply to dave_59:

rand bit [3:0] [3:0] p[];
rand bit [3:0] [31:0] q[]
rand bit [31:0] x;
rand bit [31:0] y;

constraint con1 {p.size == (x+y)/4 ;} //these x and y are fixed values setting from the sequence as 200 and 40 (by using `uvm_do_with(req,x==200;y==40;))
constraint con2 {q.size == x+y)/4 ;}

constraint con3 {foreach(p[i,j,k])
{
if(p[i][j][k] == 1'b1)
{
q[i][j][((k+1)*8 - 1)-:8] inside {0,1,2,4,8,16,32,64,128} ;
}else
{
!(q[i][j][((k+1)*8 - 1)-:8] inside {0,1,2,4,8,16,32,64,128});
}
}
constraint con4 {solve p before q;}
constraint con5 {p.sum with ($countones(item) == x*4);}

//randomization got failed becausep.sum means it will give sum of all the elements but not the number of ones in the array.

The above constraints are wrote in my transaction packet.please help me out to generate no.of ones and no.of zero’s in array should be as per my requirement

ex : bit position 0 1 2 3
                  0 1 1 0 --> 0
                    .
                    .
                    .
                  1 0 0 1 --> 59

the number of ones in the above array is equal to x value it is same for rest of 3 packed arrays.

Please any body can help me to resolve this problem?

Thanks,
Vamshi