I want to make 5x5 matrix all diagonal elements zero . Written below constraint but getting runtime error

SystemVerilog
1

Runtime Error-
Failure: C:/questasim64_10.4e/examples/matrix_gen1.sv(16): Invalid random variable in index expression for constraint.

Time: 0 ns Iteration: 0 Process: /matrix_gen1/#INITIAL#27 File: C:/questasim64_10.4e/examples/matrix_gen1.sv

Code -

class matrix_NxN ;

rand bit [3:0] a [] [ ] ;   // Dynamic array .lets consider N=5 ;

constraint c1 { a.size() == 5 ; }   // Constraing the row of 2D matrix 

constraint c2 { foreach (a[i]) {   // Constraing the coloumn of 2D matrix 
a[i].size() == 5 ; }
}

constraint c3 { foreach (a[i,j]) {
if (i==j) a[i][j] ==0 ; }
}

constraint c4 { foreach (a[i,j]) {
 a[i][a.size()-1-i] == 0 ; }
}



endclass


module matrix_gen1 ;
matrix_NxN mat_h ;

initial begin
mat_h = new();
repeat (2) begin 
mat_h.randomize();
$display("Matrix =  \n");
for (int i=0 ; i<5 ; i++) begin 
$display("%p\n",mat_h.a[i]);
end
end 
end 

endmodule

Can somebody help in resolving this error ?

2

Use proper code formatting (use triple-back-ticks ``` and end with ``` )

Your code seems to run fine on recent QU and other tools.

3

Below constraint c4 is updated like this .

constraint c4 { foreach (a[i,j]) {
a[i][4-i] == 0 ; }
}

With this I am getting correct results -
Matrix =

# 
# '{0, 4, 1, 2, 0}
# 
# '{15, 0, 14, 0, 2}
# 
# '{1, 2, 0, 11, 2}
# 
# '{4, 0, 8, 0, 5}
# 
# '{0, 6, 15, 13, 0}

but here 4 value is hardcoded . I wanted to generalize hardcoded stuffs to {a[i][a.size()-1-i] == 0 ; }
But I am getting run time errors . I think *triple-back-ticks and end with ** is not supported in system verilog . if you have any example you can share .

4

@ajitgangad_2, Srini was referring to formatting the code in your post in the forum with triple backticks.
```verilog
constraint c4 { foreach (a[i,j]) {
```
shows up as

constraint c4 { foreach (a[i,j]) {

If you want the 2 diagonal elements to be 0, use the following

constraint c4 { foreach (a[i]) {
          a[i][i] == 0;            // [0][0], [1][1]. [2][2], [3][3], [4][4]
          a[i][a.size()-1-i] == 0; // [0][4], [1][3], [2][2], [3][1], [4][0]
}
5

Thanks @dave_59 . I will use mentioned formatting while keeping post .

a[i][a.size()-1-i] == 0;

above mentioned constraints is giving below run time error-
Failure: C:/questasim64_10.4e/examples/matrix_gen1.sv(17): Invalid random variable in index expression for constraint.
How can I fix this error ?

6

You are using an extremely old version of a tool. Your code works fine with all SystemVerilog simulators on www.edaplayground.com.

7

Thanks @dave_59 . its working fine with latest Version of tools on http://www.edaplayground.com/ . Thanks for your help .