I have been trying to solve this constraints problem given below

SystemVerilog
, ,
2

In reply to hsam:

@hsam, your logic wont work for all seeds.

class packet;
  
  rand bit[9:0] matrix[9:0];

  constraint c2{
    foreach(matrix[ii,])
      $countones(matrix[ii]) == 2; 
  }
   
endclass : packet

module test;
  
  packet pkt;
  int b=0,w=0;
  
  initial begin
    pkt = new();
    pkt.randomize();
   
    foreach(pkt.matrix[ii,])
      $display("%10b", pkt.matrix[ii]);
  
       
  end
  
  
endmodule