I couldn't understand how display and monitor are working in initial block, how j =10 is coming as it would not be able to go in to loop when i =10?

SystemVerilog
2

In reply to ejaz_parvez:

For loops are 0 delay loops so they do not consume time or simulation steps. The monitor task is executed at the end of the time steps not in active region.

So your first loop will execute in active region (where display are executed) but the monitor is executed only at the really end where the loop itself is completely finished. So you see only the last one (10).