In reply to kuldeep_b:
($fell(RST),reset_deassert_time = $time) |-> (##[1:100] $rose(CLK),$display("time = %t",$time)) ##0(($time - reset_deassert_time) > worst_reset_delay_path);
// is of the form
expr1 |-> ##[1:100] expr2 ##0 expr3;
// That is equivalent to
expr1 |-> ##1 expr2 ##0 expr3 or // T1
##2 expr2 ##0 expr3 or // T2
...
##100 expr2 ##0 expr3; // T3
// Thus, if in T1 ##1 expr2==1 and expr3==0, that thread is ignored because of the "or"
// Thus, if in T2 ##1 expr2==1 and expr3==0, that thread is ignored because of the "or"
// ...
// The FIX
expr1 |-> first_match(##[1:100] expr2) ##0 expr3;
// For your property
property reset_to_clk_start_delay(CLK,RST) ;
realtime reset_deassert_time ; // <<<<<<<<< Use realtime
@(posedge top_clk_491)
disable iff(ccr_disable)
($fell(RST),reset_deassert_time = $realtime) |-> // <<<<<< Use $realtime
first_match( (##[1:100] $rose(CLK),$display("time = %t",$time)) ) ##0
(($time - reset_deassert_time) > worst_reset_delay_path);
endproperty
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Alternative for Complex Assertions
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- SVA in a UVM Class-based Environment
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