How to write the assertion to check the valid slave access by master

SystemVerilog
1

HI,

Could anyone suggest me , how to write the assertion for below scenario :

  1. checking the master to valid slave access.
  2. I have 10 different slave slave . (lets say slave 1 address is = 'h8000_0000 - 'h8000_ffff ,slave 2 address is 'h8001_0000 - 'h8001_ffff so on …)
  3. Each slave have APB interface.
    I want to check if master initiate the transaction to slave’s . it should go to respective slave’s only , not the other slave’s (meaning is master address bus = 'h8000_0000 it should go to only slave 1 not any other slave 1-9, if so it should flag error based on p_sel , p_enable and p_write signal assert)

Thanks

2

That’s usually your address decoder verification. Assuming you have a psel_vector from that decoder, something like:

   ahb_master_addr inside ['h8000_0000:'h8000_ffff] |=> psel_vec == 10'h01;
   ahb_master_addr inside ['h8001_0000:'h8001_ffff] |=> psel_vec == 10'b0000_0000_10;

Didn’t compile - so will need tweaks/syntatic fixes.