How to write SVA assumption

SystemVerilog
3

In reply to dplumb_amd:


Updated as local is reserved word. 
create the common property 
property drive_const(sig) ;
bit local_val ;
@(posedge clk) //
($fell(HDA_audio_stream_data.audio_enable), local_val = sig) |=> (sig == local_val)[*10]
endproperty 

assume property(drive_const((HDA_audio_stream_control.codec_dto_base))
assume property(drive_const((HDA_audio_stream_control.codec_dto_multi))
assume property(drive_const((HDA_audio_stream_control.codec_dto_div))