In reply to n347:
Do you think I can consider such assertions in my testbench?
There is a saying that ALL ROADS LEAD TO ROME.
- The word “assertion” is only a testimony that a property (or something) is true.
- The techniques in specifying an assertion in SystemVerilog include SVA and plain SystemVerilog code.
- SVA is constrained to be in modules, checkers, or interfaces.
- In my paper SVA Alternative for Complex Assertions I demonstrate a technique to emulate SVA anywhere in the design environment, including classes.
https://verificationacademy.com/news/verification-horizons-march-2018-issue - In the next 2020 issue of the Verification Horizons I believe that my next paper Understanding the SVA Engine Using fork-join Model will be published.
In any case, the point that I am making is that if your verification environment is in a class, then use SVA model emulation using tasks. The paper http://systemverilog.us/papers/sva4scoreboarding.pdf demonstrates how SVA is used to trigger the needed functions to do complex computations and verification. But in the end, it all boils down to the same thing. It’s interesting that my model has a lot of similarities to your requirements.
Thus, yes, you can use a similar approach for your verification.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment