How to write SV assertion which checks a field in register remines unchanged after boot sequence?

SystemVerilog
1

Hi VA,

Assume we have a register in the DUT, that after a boot-sequence is configured to specific value.
We would like to check this value remines unchanged till the end of simulation.
How would you suggest to code a check/assertion for it without running the assertion each clock cycle (performance vise)?
Checking that the value is the same only in the $finish event of simulation is not enough, in-case it flipped few times during the simulation but eventually simulation ended with the register having exact value that was written to it in the boot-sequence.

Thanks,
Michael

2

As long as there are no potential glitches in the register, you could write

initial begin
   // wait here for boot sequence to complete
   //  [insert your code here]
  @path_to_register assert(0) else $error("register has changed");
end

But if you need to look at the sampled value of the register field, there is no getting around checking each clock cycle.

2 Likes
3

Hi Dave,

Thanks for the answer.
First time I see code example like that.

Just to make sure I got the idea:
@path_to_register
Is an event which would be triggered when register.field will be modified?

4

@signal waits for signal to change its value.