How to write constraints on 2D arrays or multi dimentional arrays?

SystemVerilog
,
2

In reply to ktheja:

This is same mentioned by Dave in this.
https://verificationacademy.com/forums/systemverilog/getting-array-values-inside-certain-range

Your A[0] is only constraint in this case. You won’t require explicit i, j.


// Code your testbench here
// or browse Examples
module top();
class transaction;
rand bit[8:0]  A[5][5] ;
// Not need
//shortint i,j;
constraint c_1 {
  foreach (A[i]) {
    foreach (A[i][j]) {
      A[i][j] == i+j; 
    }
  }
}
endclass
 
transaction tr;
initial begin
tr = new();
tr.randomize();
$display ("Array is %p",tr.A);
 
end
endmodule

//Results
# vsim -voptargs=+acc=npr
# run -all
# Array is '{'{0, 1, 2, 3, 4}, '{1, 2, 3, 4, 5}, '{2, 3, 4, 5, 6}, '{3, 4, 5, 6, 7}, '{4, 5, 6, 7, 8}}
# exit
# End time: 11:05:40 on Sep 17,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 2
Done

Thanks!